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this is information on a product in full production. january 2015 docid025850 rev 5 1/39 m24c08-a125 automotive 8-kbit serial i2c bus eeprom with 1 mhz clock datasheet - production data features ? compatible with all i 2 c bus modes ?1 mhz ? 400 khz ? 100 khz ? memory array ? 8 kbits (1024 bytes) of eeprom ? page size: 16 bytes ? additional write lockable page (identification page) ? extended temperature and voltage ranges ? -40 c to 125 c; 1.8 v to 5.5 v ? schmitt trigger inputs for noise filtering ? short write cycle time ? byte write within 4 ms ? page write within 4 ms ? write cycle endurance ? 4 million write cycles at 25 c ? 1.2 million write cycles at 85 c ? 600 k write cycles at 125 c ? data retention ? 50 years at 125 c ? 100 years at 25 c ? esd protection (human body model) ? 4000 v ? packages ? rohs compliant and halogen-free (ecopack2 ? ) so8 (mn) tssop8 (dw) wfdfpn8 (mf) 2 x 3 mm 169 mil width 150 mil width www.st.com
contents m24c08-a125 2/39 docid025850 rev 5 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 chip enable (e2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 write control (wc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 v ss (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.3 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.4 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.5 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6 identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.3 write identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.4 lock identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.5 minimizing write delays by polling on ack . . . . . . . . . . . . . . . . . . . . . . 19 4.2 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.1 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.2 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.3 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.4 read identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.5 read the lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.6 acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 docid025850 rev 5 3/39 m24c08-a125 contents 3 5 application design recommendati ons . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.1 operating supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.3 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 error correction code (ecc x 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 list of tables m24c08-a125 4/39 docid025850 rev 5 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. significant address bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. device identification code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 6. operating conditions (voltage range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 7. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 8. input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 9. cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 10. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 11. 400 khz ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 12. 1 mhz ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 13. tssop8 ? 8-lead thin shrink small outline, pa ckage mechanical data. . . . . . . . . . . . . . . . 32 table 14. so8n ? 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . . . . . . 33 table 15. wfdfpn8 (mlp8) ? 8-lead thin fine pitch dual flat package no lead 2 x 3 mm, mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 16. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 17. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 docid025850 rev 5 5/39 m24c08-a125 list of figures 5 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. write mode sequences with wc = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. write mode sequences with wc = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 figure 8. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 figure 10. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 11. maximum r bus value versus bus parasitic capacitance c bus ) for an i 2 c bus at maximum frequency f c = 1mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 12. ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 13. tssop8 ? 8-lead thin shrink small outline, pa ckage outline . . . . . . . . . . . . . . . . . . . . . . . 32 figure 14. so8n ? 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 33 figure 15. wfdfpn8 (mlp8) ? 8-lead thin fine pitch dual flat package no lead 2 x 3 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 description m24c08-a125 6/39 docid025850 rev 5 1 description the m24c08-a125 is a 8-kbit se rial eeprom automotive grade device operating up to 125 c. the m24c08-a125 is comp liant with the very high level of reliability defined by the automotive standard aec-q100 grade 1. the device is accessed by a simple serial i 2 c compatible interface running up to 1 mhz. the memory array is based on advanced true eeprom technology (electrically erasable programmable memory). the m24c08-a125 is a byte-alterable memory (1024 8 bits) organized as 64 pages of 16 bytes in which th e data integrity is si gnificantly improved with an embedded error correction code logic. the m24c08-a125 offers an additional identifica tion page (16 bytes) in which the st device identification can be read. this page can al so be used to store sensitive application parameters which can be later permanently locked in read-only mode. figure 1. logic diagram - 3 6 7 # # o n t r o l l o g i c ( i g h v o l t a g e g e n e r a t o r ) / s h i f t r e g i s t e r ! d d r e s s r e g i s t e r a n d c o u n t e r $ a t a r e g i s t e r p a g e 8 d e c o d e r 9 d e c o d e r ) d e n t i f i c a t i o n p a g e % i 3 # , 3 $ ! docid025850 rev 5 7/39 m24c08-a125 description 38 figure 2. 8-pin package connections 1. see section 9: package mechanical data for package dimensions, and how to identify pin 1. table 1. signal names signal name function direction e2 chip enable input sda serial data i/o scl serial clock input wc write control input v cc supply voltage - v ss ground - 0 6 9 ^ s ^ ^ ^ > t e e s ? ? ? e ? ? signal description m24c08-a125 8/39 docid025850 rev 5 2 signal description 2.1 serial clock (scl) the signal applied on this input is used to stro be the data available on sda(in) and to output the data on sda(out). 2.2 serial data (sda) sda is an input/output used to transfer data in or out of the device. sda(out) is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull up resistor must be connected between sda and v cc ( figure 10 and figure 11 indicate how to calculate the value of the pull-up resistor). 2.3 chip enable (e2) this input signal is used to set the value that is to be looked for on the bit b3 of the device select code (see table 2 ). these inputs must be tied to vcc or vss to esta blish the device select code , as shown in figure 3 . when not connected (left floating), these inputs are read as low (0). figure 3. device select code 2.4 write control (wc ) this input signal is useful for protecting the entire contents of the memory from inadvertent write operations. write operations are disa bled to the entire memory array when write control (wc ) is driven high. write operations are enabled when write control (wc ) is either driven low or left floating. when write control (wc ) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. ! i 6 # # - x x x 6 3 3 % i 6 # # - x x x 6 3 3 % i docid025850 rev 5 9/39 m24c08-a125 signal description 38 2.5 v ss (ground) v ss is the reference for the v cc supply voltage. 2.6 supply voltage (v cc ) v cc is the supply voltage pin. device operation m24c08-a125 10/39 docid025850 rev 5 3 device operation the device supports the i 2 c protocol (see figure 4 ). the i 2 c bus is controlled by the bus master and the device is always a slave in all communications. the device (bus master or a slave) that sends data on to the bus is defined as a transmitter; the device (bus master or a slave) is defined as a receiver when reading the data. figure 4. i 2 c bus protocol 3 # , 3 $ ! 3 # , 3 $ ! 3 $ ! 3 4 ! 2 4 # o n d i t i o n 3 $ ! ) n p u t 3 $ ! # h a n g e ! ) " 3 4 / 0 # o n d i t i o n - 3 " ! # + 3 4 ! 2 4 # o n d i t i o n 3 # , - 3 " ! # + 3 4 / 0 # o n d i t i o n docid025850 rev 5 11/39 m24c08-a125 device operation 38 3.1 start condition start is identified by a falling edge of serial da ta (sda) while serial clock (scl) is stable in the high state. a start condition must prece de any data transfer instruction. the device continuously monitors (except during a writ e cycle) serial data (sda) and serial clock (scl) for a start condition. 3.2 stop condition stop is identified by a rising edge of serial da ta (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a stop condition at the end of a write instruction triggers the internal write cycle. 3.3 data input during data input, the device samples serial da ta (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low. 3.4 acknowledge bit (ack) the acknowledge bit is used to indicate a succ essful byte transfer. the bus transmitter, whether it be bus master or slave device, releas es serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits. device operation m24c08-a125 12/39 docid025850 rev 5 3.5 device addressing to start communication between the bus master and the slave device, the bus master must initiate a start condition. follo wing this, the bus master sends the device select code, as shown in table 2 . the device select code consists of a 4-bit de vice type identifier and a chip enable address (e2). a device select code handling any value other than 1010b (to select the memory) or 1011b (to select the identification page) is not acknowledged by the memory device. up to two memory devices can be connected on a single i2c bus. when the device select code is received, the memory device only respo nds if the chip enable address is the same as the value decoded on the e2 input. the 8th bit is the read/write bit (rw). this bit is set to 1 for read and 0 for write operations. if the memory device does not match the device se lect code, it deselects itself from the bus, and enters the standby mode. if the memory device matches the device se lect code, the corresponding memory device gives an acknowledgment on serial data (s da) during the 9th scl clock period. once the memory device has acknowledged the device select code, the memory device waits for the master to send the address byte. the memory device responds to the address byte with an acknowledge bit. table 2. device select code device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable address (2) 2. x bit is a don?t care bit rw b7 b6 b5 b4 b3 b2 b1 b0 when accessing the memory 1010e2a9a8rw when accessing the identification page 1011e2xxrw docid025850 rev 5 13/39 m24c08-a125 device operation 38 note: a: significant address bit. x: bit is don?t care. table 3. significant address bits memory (device type identifier = 1010b) identification page (device type identifier = 1011b) random address read write read identification page write identification page lock identification page read lock status most significant address bits b2 (1) a9 a9 x x x see section 4.2.5 b1 (1) a8 a8 x x x address byte b7 a7 a7 0 0 1 b6 a6 a6 x x x b5 a5 a5 x x x b4 a4 a4 x x x b3 a3 a3 a3 a3 x b2 a2 a2 a2 a2 x b1 a1 a1 a1 a1 x b0 a 0 a 0 a 0 a 0 x 1. address bits defined inside the deviceselect code (see table 2 ) device operation m24c08-a125 14/39 docid025850 rev 5 3.6 identification page the m24c08-a125 offers an identification page (16 bytes) in addition to the 8-kbit memory. the identification page contains two fields: ? device identification code: the first three bytes are programmed by stmicroelectronics with the device identification code, as shown in table 4 . ? application parameters: the bytes after the de vice identification code are available for application specific data. note: if the end application does not need to read the device identification code, this field can be overwritten and used to store application-spec ific data. once the app lication-specific data are written in the identification page, the whol e identification page should be permanently locked in read-only mode. the instructions read, write and lock identification page are detailed in section 4: instructions . table 4. device identification code address in identification page content value 00h st manufacturer code 20h 01h i 2 c family code e0h 02h memory density code 0ah ( 8 -kbit) docid025850 rev 5 15/39 m24c08-a125 instructions 38 4 instructions 4.1 write operations for a write operation, the bus master sends a start condition followed by a device select code with the r/w bit reset to 0. the device acknowledges this, as shown in figure 5 , and waits for the master to send the address byte with an acknowledge bit, and then waits for the data byte. when the bus master generates a stop condit ion immediately after a data byte ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal write cycle t w is then triggered. a stop condition at any ot her time slot does not trigger the internal write cycle. during the internal write cycle, serial data (s da) is disabled internally, and the device does not respond to any requests. after the successful completion of an internal write cycle (t w ), the device internal address counter is automatically increment ed to point to the next byte after the last modified byte. if the write control input (wc) is driven high, the write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in figure 6 . instructions m24c08-a125 16/39 docid025850 rev 5 4.1.1 byte write after the device select code and the address by te, the bus master sends one data byte. if the addressed location is write-protected, by write control (wc ) being driven high, the device replies with noack on the received data byte, and the location is not modified (see figure 6 ). if, instead, the addressed location is not write-protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 5 . figure 5. write mode sequences with wc = 0 (data write enabled) 3 t o p 3 t a r t " y t e 7 r i t e $ e v 3 e l e c t " y t e a d d r e s s $ a t a i n 7 # 3 t a r t 0 a g e 7 r i t e $ e v 3 e l e c t " y t e a d d r e s s $ a t a i n $ a t a i n 7 # $ a t a i n ! ) c 0 a g e 7 r i t e c o n t g d 7 # c o n t g d 3 t o p $ a t a i n . ! # + 2 7 ! # + ! # + ! # + ! # + ! # + ! # + 2 7 ! # + ! # + docid025850 rev 5 17/39 m24c08-a125 instructions 38 4.1.2 page write the page write mode allows up to n (a) bytes to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, a9/a4, ar e the same. if more bytes are se nt than will fit up to the end of the page, a condition known as ?roll-over? occurs. in case of roll-over, the first bytes of the page are overwritten. note: the bus master sends from 1 to n (1) bytes of data, each of which is acknowledged by the device if write control ( wc ) is low. if write control ( wc ) is high, the contents of the addressed memory location are not modified, and each data byte received by the device is not acknowledged, as shown in figure 6 . after each byte is transferred, the internal byte address counter is incremented. the transfer is terminated by the bus master generating a stop condition. figure 6. write mode sequences with wc = 1 (data write inhibited) a. n is the number of bytes in a page. 3 t o p 3 t a r t " y t e 7 r i t e $ e v s e l e c t " y t e a d d r e s s $ a t a i n 7 # 3 t a r t 0 a g e 7 r i t e $ e v s e l e c t " y t e a d d r e s s $ a t a i n $ a t a i n 7 # $ a t a i n ! ) d 0 a g e 7 r i t e c o n t g d 7 # c o n t g d 3 t o p $ a t a i n . ! # + ! # + . / ! # + 2 7 ! # + ! # + . / ! # + . / ! # + 2 7 . / ! # + . / ! # + instructions m24c08-a125 18/39 docid025850 rev 5 4.1.3 write identification page the identification page (16 bytes) is an additi onal page which can be written and (later) permanently locked in read-only mode. it is writ ten by issuing the write identification page instruction. this instruction us es the same protocol and format as page write (into memory array), except for the following differences: ? device type identifier = 1011b ? most significant address bits a9/a4 are don 't care, except for address bit a7 which must be ?0?. least significant address bits a3/a0 define the byte location inside the identification page. if the identification page is locked, the data bytes transferred during the write identification page instruction are not acknowledged (noack). 4.1.4 lock identification page the lock identification page instruction (lock id) permanently locks the identification page in read-only mode. the lock id instruction is si milar to byte write (into memory array) with the following specific conditions: ? device type identifier = 1011b ? address bit a7 must be ?1?; all other address bits are don't care ? the data byte must be equal to the binary value xxxx xx1x, where x is don't care docid025850 rev 5 19/39 m24c08-a125 instructions 38 4.1.5 minimizing write delays by polling on ack the maximum write time (t w ) is shown in ac characteristics tables in section 8: dc and ac parameters , but the typical time is shorter. to ma ke use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 7 , is: ? initial condition: a write cycle is in progress. ? step 1: the bus master issues a start condi tion followed by a device select code (the first byte of the new instruction). ? step 2: if the device is bu sy with the internal write cycl e, no ack will be returned and the bus master goes back to step 1. if t he device has terminated the internal write cycle, it responds with an ack, indicating th at the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). figure 7. write cycle polling flowchart using ack t?]? ?o ]v ??}p??? $ , h e?? k???]}v ]? ???]vp ?z uu}?? ^??? }v]?]}v ] ?o? ]?z z t a < ???v z ^ e k z ^ e k z ^??? ^?}? ? (}? ?z t?]? ???]}v ' h y l f h v h o h f w z l w k 5 : ^v ??? v z] < z ^ e k 6 w d u w & |